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19-2617; Rev 1; 12/02
Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers MAX9386/MAX9387/MAX9388
General Description
The MAX9386/MAX9387/MAX9388 are fully differential, high-speed, low-jitter ECL/PECL multiplexers (muxes) with output buffer(s). The devices are designed for clock-and-data distribution applications, and feature extremely low propagation delays (318ps, typ) and output-to-output skews (3.9ps, typ). The MAX9386 is a 5:1 mux with a single output buffer. The MAX9387 is a 5:1 mux with dual output buffers, and is intended for use in redundant systems. The MAX9388 is a 4:1 mux with a single output buffer, and is pin compatible with the MC100EP57. Three single-ended select inputs, SEL0, SEL1, and SEL2, control the mux function on the MAX9386/ MAX9387. The MAX9388 has two select inputs, SEL0 and SEL1. The mux select inputs are compatible with ECL/PECL logic, and are internally referenced to the on-chip output VBB, nominally VCC - 1.425V. The select inputs accept signals between VCC and VEE. Internal pulldowns to VEE ensure a low-default condition if the select inputs are left open. The differential inputs D_, D_ can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference output VBB. All the differential inputs have internal bias and clamping circuits that ensure low-default output states when the inputs are left open. The MAX9386/MAX9387/MAX9388 operate with a wide supply range | V CC - V EE| of 2.375V to 5.5V. The MAX9386/MAX9388 are offered in 20-pin TSSOP and QSOP packages. The MAX9387 is offered in 24-pin TSSOP and QSOP packages. o 318ps (typ) Propagation Delay o >2.7GHz Toggle Frequency o 0.3ps(RMS) Random Jitter o <14ps (max) at +25C Output-to-Output Skew (MAX9387) o -2.375V to -5.5V Supplies for Differential LVECL/ECL o +2.375V to +5.5V Supplies for Differential LVPECL/PECL o Outputs Low for Open Inputs o Dual Output Buffers (MAX9387) o Pin Compatible with MC100EP57 (MAX9388EUP) o >2kV ESD Protection (Human Body Model)
Features
Ordering Information
PART MAX9386EUP TEMP RANGE PINPACKAGE SELECTION 5:1 mux with 1 output buffer 5:1 mux with 1 output buffer
-40C to +85C 20 TSSOP
MAX9386EEP* -40C to +85C 20 QSOP
Ordering Information continued at end of data sheet. *Future product--contact factory for availability.
Pin Configurations
TOP VIEW
DO 1 DO 2 D1 3 D1 4 D2 5 D2 6 D3 7 D3 8 D4 9 D4 10 20 VCC 19 SEL2 18 SEL1 17 SEL0
Applications
High-Speed Telecom and Datacom Applications Central Office Backplane Clock Distribution DSLAM/DLC
MAX9386
16 Q 15 Q 14 VCC 13 VBB1 12 VBB2 11 VEE
TSSOP/QSOP
Pin Configurations continued at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers MAX9386/MAX9387/MAX9388
ABSOLUTE MAXIMUM RATINGS
VCC - VEE ...............................................................-0.3V to +6.0V Inputs (D_, D_, SEL_) to VEE ......................-0.3V to (VCC + 0.3V) D_ to D_ ..............................................................................3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA VBB_ Sink/Source Current ...............................................600A Continuous Power Dissipation (TA = +70C) 20-Lead TSSOP (derate 11.0mW/C above +70C) ....880mW JA in Still Air ...........................................................+91C/W JC ...........................................................................+20C/W 24-Lead TSSOP (derate 12.2mW/C above +70C) ....976mW JA in Still Air ...........................................................+82C/W JC ...........................................................................+15C/W 20-Lead QSOP (derate 9.1mW/C above +70C) .......727mW JA in Still Air .........................................................+110C/W JC ...........................................................................+34C/W 24-Lead QSOP (derate 9.5mW/C above +70C) .......762mW JA in Still Air .........................................................+105C/W JC ...........................................................................+34C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (D_, D_, Q_, Q_, SEL_, VBB_) .............2kV Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 2.375V to 5.5V, outputs loaded with 50 1% to VCC - 2V. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1-4)
PARAMETER SYMBOL CONDITIONS -40C MIN TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX UNITS
INPUT (D_, D_, SEL_) Single-Ended Input High Voltage Single-Ended Input Low Voltage Differential Input High Voltage Differential Input Low Voltage VIH VBB connected to the unused input (Figure 1) VBB connected to the unused input (Figure 1) Figure 1 Figure 1 VCC - VEE < 3.0V VCC - VEE 3.0V VCC 1.225 VCC - VCC 0.880 1.225 VCC - VCC 0.880 1.225 VCC 0.880 V
VIL
VCC 1.945 VEE + 1.2 VEE 0.095 0.095 -100
VCC - VCC 1.625 1.945 VCC VCC 0.095 VCC VEE VEE + 1.2 VEE 0.095
VCC - VCC 1.625 1.945 VCC VCC 0.095 VCC VEE VEE + 1.2 VEE 0.095
VCC 1.625 VCC VCC 0.095 VCC VEE 3.000 +100
V
VIHD VILD
V V
Differential Input Voltage Input Current
VIHD - VILD Figure 1
V
3.000 0.095 +100 -100
3.000 0.095 +100 -100
IIN
VIH, VIL, VIHD, VILD
A
2
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Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = 2.375V to 5.5V, outputs loaded with 50 1% to VCC - 2V. Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1-4)
PARAMETER OUTPUT (Q_, Q_) Single-Ended Output High Voltage Single-Ended Output Low Voltage Differential Output Voltage VOH Figure 2 VCC 1.145 VCC - VCC 0.895 1.145 VCC - VCC 0.895 1.145 VCC 0.895 V SYMBOL CONDITIONS -40C MIN TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX UNITS
MAX9386/MAX9387/MAX9388
VOL
Figure 2
VCC 1.945 650 830
VCC - VCC 1.695 1.945 650 840
VCC - VCC 1.695 1.945 650 840
VCC 1.695
V
VOH - VOL Figure 2
mV
REFERENCE OUTPUT (VBB_ ) Reference Voltage Output POWER SUPPLY MAX9386 Supply Current (Note 6) IEE MAX9387 MAX9388 34 40 31 50 60 47 36 42 33 50 60 47 38 45 35 50 60 47 mA VBB1, VBB2 IBB1 + IBB2 = 0.5mA (Note 5) VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC 1.525 1.425 1.325 1.525 1.425 1.325 1.525 1.425 1.325 V
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = 2.375V to 5.5V, outputs loaded with 50 1% to VCC - 2V, VIHD - VILD = 0.15V to 1V, fIN 2.5GHz input duty cycle = 50%, input transition time = 125ps (20% to 80%). Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 622MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.) (Note 7)
PARAMETER Differential Input-to-Output Delay SEL_-to-Output Delay Output-toOutput Skew Input-to-Output Skew Part-to-Part Skew SYMBOL tPLHD, tPHLD tPLH2, tPHL2 tSKOO tSKIO tSKPP CONDITIONS -40C MIN 222 TYP 309 MAX 377 MIN 238 +25C TYP 318 MAX 395 MIN 254 +85C TYP 333 MAX 431 UNITS
Figure 2
ps
Figure 4, input transition time = 500ps (20% to 80%) (Note 8) MAX9387 only, Figure 5 (Note 9) Figure 6 (Note 10) (Note 11) 3.9 7.3
1.64
1.4
1.6
ns
26 53 111
3.9 7.7
14 50 130
8.0 8.3
26 50 133
ps ps ps
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3
Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers MAX9386/MAX9387/MAX9388
AC ELECTRICAL CHARACTERISTICS (continued)
VCC - VEE = 2.375V to 5.5V, outputs loaded with 50 1% to VCC - 2V, VIHD - VILD = 0.15V to 1V, fIN 2.5GHz input duty cycle = 50%, input transition time = 125ps (20% to 80%). Typical values are at VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 622MHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.) (Note 7)
PARAMETER Added Random Jitter (Note 12) Added Deterministic Jitter (Note 12) Switching Frequency Select Toggle Frequency Output Rise and Fall Time (20% to 80%) SYMBOL CONDITIONS Clock pattern PRBS 223 - 1 fIN = 156MHz fIN = 622MHz fIN = 2.5GHz fIN = 156Mbps fIN = 622Mbps 2.7 100 TDJ -40C MIN TYP 0.3 0.3 0.3 33 21 MAX 1.15 1.15 1.15 95 61 2.7 100 MIN +25C TYP 0.3 0.3 0.3 33 21 MAX 1.15 1.15 1.15 95 61 2.7 100 MIN +85C TYP 0.3 0.3 0.3 33 21 MAX 1.15 1.15 1.15 95 psP-P 61 GHz MHz ps(RMS) UNITS
tRJ
fMAX fSEL
VOH - VOL 300mV, Figure 2
t R , tF
Figure 2
67
105
138
74
117
155
81
128
165
ps
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10:
Measurements are made with the device in thermal equilibrium. Current into an I/O pin is defined as positive. Current out of an I/O pin is defined as negative. DC parameters production tested at TA = +25C and guaranteed by design over the full operating temperature range. Single-ended data input operation using VBB_ is limited to (VCC - VEE) 3.0V. Use VBB_ only for inputs that are on the same device as the VBB_ reference. All pins open except VCC and VEE. Guaranteed by design and characterization. Limits are set at 6 sigma. Measured from the 50% point of the input signal with the 50% point equal to VBB, to the 50% point of the output signal. Measured between outputs of the same part at the signal crossing points for a same-edge transition. Measured between input-to-output paths of the same part at the signal crossing points for a same-edge transition of the differential input signal. Note 11: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 12: Device jitter added to the differential input signal.
4
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Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers
Typical Operating Characteristics
(VCC - VEE = 3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, outputs loaded with 50 1% to VCC - 2V, fIN = 1.5GHz, input duty cycle = 50%, input transition time = 125ps (20% to 80%), unless otherwise noted.)
MAX9386/MAX9387/MAX9388
SUPPLY CURRENT (IEE) vs. TEMPERATURE
MAX9386 toc01
OUTPUT AMPLITUDE (VOH - VOL) vs. FREQUENCY
MAX9386 toc02
OUTPUT RISE/FALL vs. TEMPERATURE
MAX9386 toc03
60 55 SUPPLY CURRENT (mA) 50 45 40 35 30 25 20 -40 -15 10 35 60
1000
150 140 RISE/FALL TIME (ps) 130 120 110 RISE 100 90 FALL
800 OUTPUT VOLTAGE (mV)
600
400
200
0 85 0 400 800 1200 1600 2000 2400 2800 TEMPERATURE (C) FREQUENCY (MHz)
-40
-15
10
35
60
85
TEMPERATURE (C)
DIFFERENTIAL PROPAGATION DELAY vs. INPUT HIGH VOLTAGE
MAX9386 toc04
DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE
MAX9386 toc05
370 360 PROPAGATION DELAY (ps) 350 340 330 320 310 300 290 280 270 1.2 1.5 1.8 2.1 2.4 2.7 tPLHD tPHLD
350 340 TRANSITION TIME (ps) 330 320 310 300 290 280 tPLHD tPHLD
3.0
-40
-15
10
35
60
85
INPUT HIGH VOLTAGE (V)
TEMPERATURE (C)
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5
Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers MAX9386/MAX9387/MAX9388
MAX9386/MAX9388 Pin Description
PIN NAME MAX9386 1 2 3 4 5 6 7 8 9 10 11 12 MAX9388 2 3 4 5 6 7 8 9 -- -- 10, 11 12 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 VEE VBB2 Noninverting Differential Input 0. Internal 250k to VCC and 150k to VEE. Inverting Differential Input 0. Internal 150k to VCC and 150k to VEE. Noninverting Differential Input 1. Internal 250k to VCC and 150k to VEE. Inverting Differential Input 1. Internal 150k to VCC and 150k to VEE. Noninverting Differential Input 2. Internal 250k to VCC and 150k to VEE. Inverting Differential Input 2. Internal 150k to VCC and 150k to VEE. Noninverting Differential Input 3. Internal 250k to VCC and 150k to VEE. Inverting Differential Input 3. Internal 150k to VCC and 150k to VEE. Noninverting Differential Input 4. Internal 250k to VCC and 150k to VEE. Inverting Differential Input 4. Internal 150k to VCC and 150k to VEE. Negative Supply Reference Output Voltage 2. Connect to the inverting or noninverting data input to provide a reference for single-ended operation. When used, bypass VBB2 to VCC with a 0.01F ceramic capacitor. Otherwise leave open. Reference Output Voltage 1. Connect to the inverting or noninverting data input to provide a reference for single-ended operation. When used, bypass VBB1 to VCC with a 0.01F ceramic capacitor. Otherwise leave open. Positive Supply. Bypass each VCC to VEE with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Inverting Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Output. Typically terminate with 50 resistor to VCC - 2V. Select Logic Input 0. Internal 120k pulldown to VEE. Select Logic Input 1. Internal 120k pulldown to VEE. Select Logic Input 2. Internal 120k pulldown to VEE. FUNCTION
13
13
VBB1
14, 20 15 16 17 18 19
1, 14 17, 20 15 16 18 19 --
VCC Q Q SEL0 SEL1 SEL2
6
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Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers
MAX9387 Pin Description
PIN NAME MAX9387 1, 18, 24 2 3 4 5 6 7 8 9 10 11 12, 13 14 VCC D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 VEE VBB2 Positive Supply. Bypass each VCC to VEE with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Noninverting Differential Input 0. Internal 250k to VCC and 150k to VEE. Inverting Differential Input 0. Internal 150k to VCC and 150k to VEE. Noninverting Differential Input 1. Internal 250k to VCC and 150k to VEE. Inverting Differential Input 1. Internal 150k to VCC and 150k to VEE. Noninverting Differential Input 2. Internal 250k to VCC and 150k to VEE. Inverting Differential Input 2. Internal 150k to VCC and 150k to VEE. Noninverting Differential Input 3. Internal 250k to VCC and 150k to VEE. Inverting Differential Input 3. Internal 150k to VCC and 150k to VEE. Noninverting Differential Input 4. Internal 250k to VCC and 150k to VEE. Inverting Differential Input 4. Internal 150k to VCC and 150k to VEE. Negative Supply Reference Output Voltage 2. Connect to the inverting or noninverting data input to provide a reference for single-ended operation. When used, bypass VBB2 to VCC with a 0.01F ceramic capacitor. Otherwise leave open. Reference Output Voltage 1. Connect to the inverting or noninverting data input to provide a reference for single-ended operation. When used, bypass VBB1 to VCC with a 0.01F ceramic capacitor. Otherwise leave open. Inverting Output 1. Typically terminate with 50 resistor to VCC - 2V. Noninverting Output 1. Typically terminate with 50 resistor to VCC - 2V. Inverting Output 0. Typically terminate with 50 resistor to VCC - 2V. Noninverting Output 0. Typically terminate with 50 resistor to VCC - 2V. Select Logic Input 0. Internal 120k pulldown to VEE. Select Logic Input 1. Internal 120k pulldown to VEE. Select Logic Input 2. Internal 120k pulldown to VEE. FUNCTION
MAX9386/MAX9387/MAX9388
15 16 17 19 20 21 22 23
VBB1 Q1 Q1 Q0 Q0 SEL0 SEL1 SEL2
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7
Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers MAX9386/MAX9387/MAX9388
VCC VIHD (MAX) VIHD - VILD VILD (MAX) VBB VIL VIH VCC
VIHD (MIN) VIHD - VILD VEE VILD (MIN) VEE
DIFFERENTIAL INPUT VOLTAGE DEFINITION
SINGLE-ENDED INPUT VOLTAGE DEFINITION
Figure 1. Input Definitions
D_ VIHD - VILD D_ tPLHD Q_ VOH - VOL Q_ tPHLD
VIHD
VILD
VOH
VOL
80% DIFFERENTIAL OUTPUT WAVEFORM 20% Q_ - Q_ tR
VOH - VOL
80% 0V (DIFFERENTIAL)
VOH - VOL
20%
tF
Figure 2. Differential Input-to-Output Propagation Delay Timing Diagram
D_ WHEN D_ = VBB VBB OR VBB D_ WHEN D_ = VBB tPLH1 Q_ VOH - VOL Q_ tPHL1
VIH
VIL
VOH
VOL
Figure 3. Single-Ended Input-to-Output Propagation Delay Timing Diagram
8
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Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers MAX9386/MAX9387/MAX9388
D_, D1 VIHD - VILD D_, D1 VILD VIH SEL_ = VIL OR OPEN SELO tPLH2 Q_ VOH - VOL Q_ VOL VBB VIL tPHL2 VOH VIHD
Figure 4. Select Input (SEL0)-to-Output (Q_, Q_) Delay Timing Diagram
Q0
Q0 Q1
Q1 tSKOO tSKOO
Figure 5. Output-to-Output Skew (tSKOO) Definition (MAX9387 Only)
D0
D0 Q0
Q0 tPLHD* D1 OR D2 OR D3 tPHLD*
D1 OR D2 OR D3 Q0
Q0 tPLHD** tSKIO = | tPLHD* - tPLHD** | OR | tPHLD* - tPHLD** | tPLHD*: MEASURED BETWEEN D0, D0 INPUT, AND OUTPUT. tPLHD**: MEASURED BETWEEN ANY OTHER INPUT AND OUTPUT. tPHLD**
Figure 6. Input-to-Output Skew (tSKIO) Definition _______________________________________________________________________________________ 9
Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers MAX9386/MAX9387/MAX9388
Detailed Description
The MAX9386/MAX9387/MAX9388 are fully differential, high-speed, and low-jitter ECL/PECL muxes with output buffer(s). The devices are designed for clock-and-data distribution applications, and feature extremely low propagation delays (318ps, typ) and output-to-output skews (3.9ps, typ). The MAX9386 is a 5:1 mux with a single output buffer. The MAX9387 is a 5:1 mux with dual output buffers, and is intended for use in redundant systems. The MAX9388 is a 4:1 mux with a single output buffer, and is pin compatible with the MC100EP57. Three single-ended select inputs, SEL0, SEL1, and SEL2, control the mux function on the MAX9386/ MAX9387. The MAX9388 has two select inputs, SEL0 and SEL1 (see Tables 1 and 2). The mux select inputs are compatible with ECL/PECL logic, and are internally referenced to the on-chip output VBB, nominally VCC 1.425V. The select inputs accept signals between VCC and VEE. Internal 120k pulldowns to VEE ensure a low default condition if the select inputs are left open, selecting the D0, D0 input. The differential inputs D, D can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference voltage VBB. The reference output voltages, VBB1 and VBB2, provide the reference voltage for single-ended operation for each mux. A single-ended input of at least VBB_ 100mV or a differential input of at least 100mV switches the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics. The maximum magnitude of the differential input from D to D is 3.0V. This limit also applies to the difference between a single-ended input and any reference voltage input. Specifications for the high and low voltages of a differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously.
Single-Ended Operation
The recommended supply voltage for single-ended operation is 3.0V to 5.5V. The differential inputs (D, D) can be configured to accept single-ended inputs when operating at supply voltages greater than 2.725V. In single-ended mode operation, the unused complementary input needs to be connected to the on-chip reference voltage, VBB, as a reference. For example, the differential D, D input is converted to a noninverting, single-ended input by connecting VBB to D and connecting the single-ended input to D. Similarly, an inverting input is obtained by connecting VBB to D and connecting the single-ended input to D. With a differential input configured as single ended (using VBB), the single-ended input can be driven to VCC or VEE or with a single-ended LVPECL/LVECL signal. In single-ended mode operation, a user must ensure that the supply voltage (VCC - V EE ) is greater than 2.725V. This is because the input high minimum level must be at (VEE + 1.2V) or higher for proper operation. The reference voltage, VBB, must be at least (VEE + 1.2V) for the same reason because it becomes the highlevel input when a single-ended input swings below it. The minimum VBB output for the MAX9386/MAX9387/ MAX9388 is (VCC - 1.38V). Substituting the minimum VBB output for (VBB = VEE + 1.2V) results in a minimum supply (VCC - VEE) of 2.725V. Rounding up to standard supplies gives the recommended single-ended operating supply ranges (VCC - VEE) of 3.0V to 5.5V. When using the VBB reference output, bypass it with a 0.01F ceramic capacitor to VCC. If not used, leave it open. The VBB reference can source or sink a total of 0.5mA (shared between VBB1 and VBB2), which is sufficient to drive five inputs.
Table 1. Mux Select Input Truth Table for MAX9386/MAX9387
SEL2 L or open L or open L or open L or open H SEL1 L or open L or open H H X SEL0 L or open H L or open H X DATA OUTPUT D0* D1 D2 D3 D4
*Default output when SEL0, SEL1, and SEL2 are left open.
Table 2. Mux Select Input Truth Table for MAX9388
SEL1 L or open L or open H H SEL0 L or open H L or open H DATA OUTPUT D0* D1 D2 D3
*Default output when SEL0 and SEL1 are left open. 10 ______________________________________________________________________________________
Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers
Applications Information
Output Termination
Terminate the outputs through 50 to VCC - 2V or use equivalent Thevenin terminations. Terminate each Q and Q output with identical termination on each for minimal distortion. When a single-ended signal is taken from the differential output, terminate both Q and Q. Ensure that output currents do not exceed the current limits as specified in the Absolute Maximum Ratings table. Under all operating conditions, the device's total thermal limits should be observed.
D0 D0 D1 D1 D2 D2 D3 D3 D4** D4** SEL0 SEL1 SEL2** 120k D_ D_ 150k VEE 150k 250k VCC 150k MUX Q0 (Q*) Q0 (Q*) Q1* Q1* VBB1 VBB2 MAX9386 MAX9387 MAX9388 VCC VEE
Functional Block Diagram
MAX9386/MAX9387/MAX9388
Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1F and 0.01F capacitors. For PECL, bypass each VCC to VEE. For ECL, bypass each VEE to VCC. Place the capacitors as close to the device as possible with the 0.01F capacitor closest to the device pins. Use multiple vias when connecting the bypass capacitors to ground. When using the VBB1 or VBB2 reference outputs, bypass each one with a 0.01F ceramic capacitor to VCC. If the VBB1 or VBB2 reference outputs are not used, they can be left open.
Traces
Circuit board trace layout is very important to maintain the signal integrity of high-speed differential signals. Maintaining integrity is accomplished in part by reducing signal reflections and skew, and increasing common-mode noise immunity. Signal reflections are caused by discontinuities in the 50 characteristic impedance of the traces. Avoid discontinuities by maintaining the distance between differential traces, not using sharp corners or using vias. Maintaining distance between the traces also increases common-mode noise immunity. Reducing signal skew is accomplished by matching the electrical length of the differential traces.
VEE
MAX9386 (*) DOES NOT HAVE Q1 AND Q1 OUTPUTS, AND MAX9388 (**) DOES NOT HAVE D4, D4, AND SEL2 INPUTS.
Ordering Information (continued)
PART TEMP RANGE PINPACKAGE SELECTION 5:1 mux with 2 output buffers 5:1 mux with 2 output buffers 4:1 mux with 1 output buffer 4:1 mux with 1 output buffer
MAX9387EUG -40C to +85C 24 TSSOP MAX9387EEG* -40C to +85C 24 QSOP
Chip Information
TRANSISTOR COUNT: 583 PROCESS: Bipolar
MAX9388EUP
-40C to +85C 20 TSSOP
MAX9388EEP* -40C to +85C 20 QSOP
*Future product--contact factory for availability.
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11
Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers MAX9386/MAX9387/MAX9388
Pin Configurations (continued)
TOP VIEW
VCC 1 DO 2 DO 3 D1 4 D1 5 D2 6 D2 7 D3 8 D3 9 VEE 10 20 VCC 19 SEL1 18 SEL0 17 VCC VCC 1 DO 2 DO 3 D1 4 D1 5 D2 6 D2 7 D3 8 D3 9 D4 10 D4 11 24 VCC 23 SEL2 22 SEL1 21 SEL0
MAX9388
16 Q 15 Q 14 VCC 13 VBB1 12 VBB2 11 VEE
MAX9387
20 Q0 19 Q0 18 VCC 17 Q1 16 Q1 15 VBB1 14 VBB2 13 VEE
TSSOP/QSOP
VEE 12
TSSOP/QSOP
12
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Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX9386/MAX9387/MAX9388
______________________________________________________________________________________
TSSOP4.40mm.EPS
13
Differential 5:1 or 4:1 ECL/PECL Multiplexers with Single/Dual Output Buffers MAX9386/MAX9387/MAX9388
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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